pingu_98/icicle
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
32-bit RISC-V system on chip for iCE40 FPGAs
96 commits 1 branch 0 tags 149 KiB
SystemVerilog 96.1%
Makefile 2.3%
C 0.9%
Assembly 0.4%
Tcl 0.3%
Find a file
Graham Edgecombe d5c87dacf6 Add MRET and WFI instruction encoding 
I'm probably going to implement a subset of the privileged ISA for
interrupt support.
2017-12-14 23:46:18 +00:00
.gitignore Store icebox_stat output in top.stat 2017-12-07 22:37:58 +00:00
clk_div.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
ice40hx8k-b-evn.pcf Add serial flash, LED and UART pins 2017-12-01 23:25:06 +00:00
Makefile Rename check target to syntax 2017-12-12 21:20:49 +00:00
progmem.s Add UART demo program 2017-12-07 22:37:59 +00:00
ram.sv Merge memory bus inputs/outputs in the port list 2017-12-12 21:15:11 +00:00
rv32.sv Merge memory bus inputs/outputs in the port list 2017-12-12 21:15:11 +00:00
rv32_alu.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_branch.sv Rename rv32_branch to rv32_branch_unit 2017-12-12 21:05:02 +00:00
rv32_decode.sv Simplify giant case statement in the decoder 2017-12-12 22:42:47 +00:00
rv32_execute.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_fetch.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_hazard.sv Rename rv32_hazard to rv32_hazard_unit 2017-12-12 21:04:33 +00:00
rv32_mem.sv Rename rv32_branch to rv32_branch_unit 2017-12-12 21:05:02 +00:00
rv32_opcodes.sv Add MRET and WFI instruction encoding 2017-12-14 23:46:18 +00:00
rv32_regs.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
sync.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
top.sv Merge memory bus inputs/outputs in the port list 2017-12-12 21:15:11 +00:00
top.ys Pass -full to opt 2017-12-08 22:29:22 +00:00
uart.sv Merge memory bus inputs/outputs in the port list 2017-12-12 21:15:11 +00:00