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32-bit RISC-V system on chip for iCE40 FPGAs
100 commits 1 branch 0 tags 149 KiB
SystemVerilog 96.1%
Makefile 2.3%
C 0.9%
Assembly 0.4%
Tcl 0.3%
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Graham Edgecombe d97f8c5e8e Add yosys-config --datdir workaround 
The yosys-git AUR package doesn't set the PREFIX variable correctly.
2017-12-15 18:35:26 +00:00
.gitignore Store icebox_stat output in top.stat 2017-12-07 22:37:58 +00:00
.gitlab-ci.yml Add yosys-config --datdir workaround 2017-12-15 18:35:26 +00:00
clk_div.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
ice40hx8k-b-evn.pcf Add serial flash, LED and UART pins 2017-12-01 23:25:06 +00:00
Makefile Add yosys-config --datdir workaround 2017-12-15 18:35:26 +00:00
progmem.s Add UART demo program 2017-12-07 22:37:59 +00:00
ram.sv Merge memory bus inputs/outputs in the port list 2017-12-12 21:15:11 +00:00
rv32.sv Merge memory bus inputs/outputs in the port list 2017-12-12 21:15:11 +00:00
rv32_alu.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_branch.sv Rename rv32_branch to rv32_branch_unit 2017-12-12 21:05:02 +00:00
rv32_decode.sv Add MRET and WFI to the decoder 2017-12-14 23:53:49 +00:00
rv32_execute.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_fetch.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
rv32_hazard.sv Rename rv32_hazard to rv32_hazard_unit 2017-12-12 21:04:33 +00:00
rv32_mem.sv Rename rv32_branch to rv32_branch_unit 2017-12-12 21:05:02 +00:00
rv32_opcodes.sv Add MRET and WFI instruction encoding 2017-12-14 23:46:18 +00:00
rv32_regs.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
sync.sv Fix compatibility with iverilog 2017-12-09 21:03:45 +00:00
top.sv Merge memory bus inputs/outputs in the port list 2017-12-12 21:15:11 +00:00
top.ys Pass -full to opt 2017-12-08 22:29:22 +00:00
uart.sv Merge memory bus inputs/outputs in the port list 2017-12-12 21:15:11 +00:00