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Add read_out signal to the memory bus

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This is required to implement reads with side effects (e.g. reading from
the UART receive buffer).
This commit is contained in:
Graham Edgecombe 2017-12-06 15:36:46 +00:00
parent 460159a392
commit 82394bce1c
3 changed files with 6 additions and 0 deletions
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2
rv32.sv
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@ -11,6 +11,7 @@ module rv32 (
input clk, input clk,
/* control out (memory bus) */ /* control out (memory bus) */
output read_out,
output [3:0] write_mask_out, output [3:0] write_mask_out,
/* data in (memory bus) */ /* data in (memory bus) */
@ -249,6 +250,7 @@ module rv32 (
.rd_write_out(mem_rd_write), .rd_write_out(mem_rd_write),
/* control out (to memory bus) */ /* control out (to memory bus) */
.read_out(read_out),
.write_mask_out(write_mask_out), .write_mask_out(write_mask_out),
/* data out */ /* data out */

2
rv32_mem.sv
View file

@ -37,6 +37,7 @@ module rv32_mem (
output rd_write_out, output rd_write_out,
/* control out (to memory bus) */ /* control out (to memory bus) */
output read_out,
output [3:0] write_mask_out, output [3:0] write_mask_out,
/* data out */ /* data out */
@ -60,6 +61,7 @@ module rv32_mem (
assign branch_pc_out = branch_pc_in; assign branch_pc_out = branch_pc_in;
assign read_out = read_in;
assign address_out = result_in; assign address_out = result_in;
always_comb begin always_comb begin

2
top.sv
View file

@ -60,6 +60,7 @@ module top (
.clk(pll_clk), .clk(pll_clk),
/* control out */ /* control out */
.read_out(mem_read),
.write_mask_out(mem_write_mask), .write_mask_out(mem_write_mask),
/* data in */ /* data in */
@ -71,6 +72,7 @@ module top (
); );
/* memory bus control */ /* memory bus control */
logic mem_read;
logic [3:0] mem_write_mask; logic [3:0] mem_write_mask;
/* memory bus data */ /* memory bus data */