32-bit RISC-V system on chip for iCE40 FPGAs

Graham Edgecombe 82394bce1c Add read_out signal to the memory bus ... This is required to implement reads with side effects (e.g. reading from the UART receive buffer).		2017-12-07 22:37:58 +00:00
.gitignore	Store icebox_stat output in top.stat	2017-12-07 22:37:58 +00:00
clk_div.sv	Replace wire with logic	2017-12-07 22:37:58 +00:00
ice40hx8k-b-evn.pcf	Add serial flash, LED and UART pins	2017-12-01 23:25:06 +00:00
Makefile	Move timing closure requirement to the flash target	2017-12-07 22:37:58 +00:00
progmem.s	Use t0 register in demo program	2017-12-07 22:37:58 +00:00
ram.sv	Add memory address decoding	2017-12-07 22:37:58 +00:00
rv32.sv	Add read_out signal to the memory bus	2017-12-07 22:37:58 +00:00
rv32_alu.sv	Remove _ops.sv files	2017-12-07 22:37:58 +00:00
rv32_branch.sv	Remove _ops.sv files	2017-12-07 22:37:58 +00:00
rv32_decode.sv	Rename rd_writeback to rd_write	2017-12-07 22:37:58 +00:00
rv32_execute.sv	Rename rd_writeback to rd_write	2017-12-07 22:37:58 +00:00
rv32_fetch.sv	Follow the standard naming/commenting conventions in hazard-related code	2017-12-07 22:37:58 +00:00
rv32_hazard.sv	Rename rd_writeback to rd_write	2017-12-07 22:37:58 +00:00
rv32_mem.sv	Add read_out signal to the memory bus	2017-12-07 22:37:58 +00:00
rv32_opcodes.sv	Add flush and stall inputs to every stage	2017-12-07 22:37:58 +00:00
rv32_regs.sv	Rename rd_writeback to rd_write	2017-12-07 22:37:58 +00:00
sync.sv	Add synchronizer module	2017-12-07 22:37:58 +00:00
top.sv	Add read_out signal to the memory bus	2017-12-07 22:37:58 +00:00
top.ys	Run abc twice to improve logic density	2017-12-07 22:37:58 +00:00
uart.sv	Add loopback UART	2017-12-07 22:37:58 +00:00