Graham Edgecombe
04dc25c5dc
Merge memory bus inputs/outputs in the port list
...
I don't think the control/data in/out split makes as much sense - it's
a convention much better suited to the pipeline stages.
2017-12-12 21:15:11 +00:00
Graham Edgecombe
22bce1bdeb
Fix compatibility with iverilog
...
This commit:
* changes the type of all output variables to logic
* splits variable declaration and assignment
* declares variables before modules that use the variables
2017-12-09 21:03:45 +00:00
Graham Edgecombe
e801556428
Replace localparams at the root level with defines
...
iverilog doesn't support localparams at the root level.
2017-12-09 10:44:39 +00:00
Graham Edgecombe
66089359fe
Make the meaning of the TX write ready status bit clearer
2017-12-07 22:37:59 +00:00
Graham Edgecombe
02909b1f98
Add receive support to the UART
2017-12-07 22:37:59 +00:00
Graham Edgecombe
4d9d405c05
Fix TX ready output
2017-12-07 22:37:59 +00:00
Graham Edgecombe
6d638404f1
Add new memory-mapped UART
...
This implementation uses a simpler state machine than the previous
version.
The receiver still needs to be implemented.
2017-12-07 22:37:59 +00:00
Graham Edgecombe
cddfd0587d
Add loopback UART
2017-12-07 22:37:58 +00:00
