Graham Edgecombe
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018faac560
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Add memory bus and move data memory to a separate module
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2017-12-07 22:37:58 +00:00 |
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Graham Edgecombe
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03ecd3a97d
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Remove unused mem_read_en output
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2017-12-07 22:37:58 +00:00 |
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Graham Edgecombe
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e7ae22bf31
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Remove _ops.sv files
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2017-12-07 22:37:58 +00:00 |
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Graham Edgecombe
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0acde319b0
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Stall the decode stage if it is waiting on a load
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2017-12-07 22:37:58 +00:00 |
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Graham Edgecombe
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86022d42a5
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Follow the standard naming/commenting conventions in hazard-related code
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2017-12-07 22:37:58 +00:00 |
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Graham Edgecombe
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eff39ad19b
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Add flush and stall inputs to every stage
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2017-12-07 22:37:58 +00:00 |
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Graham Edgecombe
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cc89d3f93a
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Replace tabs with spaces in rv32_mem.sv
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2017-12-07 22:37:58 +00:00 |
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Graham Edgecombe
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dd6e01fb5c
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Move result/mem_read_value mux to the mem stage
This should reduce the logic required to forward the writeback rd_value
to the execute stage, which is on the critical path.
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2017-12-07 22:37:58 +00:00 |
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Graham Edgecombe
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871e1f4a32
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Add LB, LBU, LH, LHU, SB and SH instructions
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2017-12-07 22:37:58 +00:00 |
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Graham Edgecombe
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e2a533babb
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Access data memory on negative clock edge
This will allow shifting, sign extension and zero extension logic to be
placed after reads, so we can add support for the LB, LBU, LH and LHU
opcodes.
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2017-12-07 22:37:58 +00:00 |
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Graham Edgecombe
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85ba0c7faa
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Remove read_value_out enable input
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2017-12-07 22:37:23 +00:00 |
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Graham Edgecombe
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bef709dc73
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Replace always with always_ff
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2017-12-02 18:29:51 +00:00 |
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Graham Edgecombe
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86f6e0eec1
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Add branching support
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2017-12-02 15:23:12 +00:00 |
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Graham Edgecombe
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4c68818134
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Add writeback stage
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2017-12-02 11:26:12 +00:00 |
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Graham Edgecombe
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3f8e64c65a
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Add memory access stage
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2017-12-02 10:22:48 +00:00 |
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