Graham Edgecombe
22bce1bdeb
Fix compatibility with iverilog
...
This commit:
* changes the type of all output variables to logic
* splits variable declaration and assignment
* declares variables before modules that use the variables
2017-12-09 21:03:45 +00:00
Graham Edgecombe
460159a392
Rename rd_writeback to rd_write
...
This is consistent with the mem_read and mem_write naming.
2017-12-07 22:37:58 +00:00
Graham Edgecombe
86022d42a5
Follow the standard naming/commenting conventions in hazard-related code
2017-12-07 22:37:58 +00:00
Graham Edgecombe
eff39ad19b
Add flush and stall inputs to every stage
2017-12-07 22:37:58 +00:00
Graham Edgecombe
efb33456f9
Add include guards
2017-12-01 23:30:33 +00:00
Graham Edgecombe
ed238e5e9b
Use -noautowire to avoid using logic in every input/output declaration
2017-12-01 18:49:48 +00:00
Graham Edgecombe
4a4dee334d
Add initial fetch/decode stages
2017-12-01 08:46:43 +00:00
