32-bit RISC-V system on chip for iCE40 FPGAs

Graham Edgecombe 2b1e0de9de Propagate mem_fence signal through the pipeline		2017-12-26 16:46:01 +00:00
.gitignore	Port example program to C	2017-12-15 20:08:55 +00:00
.gitlab-ci.yml	Add yosys-config --datdir workaround	2017-12-15 18:35:26 +00:00
bus_arbiter.sv	Combine the instruction and data buses	2017-12-25 23:33:53 +00:00
clk_div.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
ice40hx8k-b-evn.pcf	Add serial flash, LED and UART pins	2017-12-01 23:25:06 +00:00
Makefile	Bump FREQ_PLL to 36 MHz again	2017-12-26 14:40:54 +00:00
progmem.c	Add new 'hello world' demo program	2017-12-26 13:46:20 +00:00
progmem.lds	Add rodata to the linker script	2017-12-25 23:42:32 +00:00
ram.sv	Swap byte order in the ram module	2017-12-26 14:15:12 +00:00
rv32.sv	Propagate mem_fence signal through the pipeline	2017-12-26 16:46:01 +00:00
rv32_alu.sv	Re-use the main adder to implement the LUI, JAL and JALR instructions	2017-12-16 12:45:43 +00:00
rv32_branch.sv	Rename rv32_branch to rv32_branch_unit	2017-12-12 21:05:02 +00:00
rv32_decode.sv	Propagate mem_fence signal through the pipeline	2017-12-26 16:46:01 +00:00
rv32_execute.sv	Propagate mem_fence signal through the pipeline	2017-12-26 16:46:01 +00:00
rv32_fetch.sv	Combine the instruction and data buses	2017-12-25 23:33:53 +00:00
rv32_hazard.sv	Combine the instruction and data buses	2017-12-25 23:33:53 +00:00
rv32_mem.sv	Switch from big- to little-endian ordering in the memory access stage	2017-12-26 13:40:55 +00:00
rv32_opcodes.sv	Add MRET and WFI instruction encoding	2017-12-14 23:46:18 +00:00
rv32_regs.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
start.s	Port example program to C	2017-12-15 20:08:55 +00:00
sync.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
top.sv	Combine the instruction and data buses	2017-12-25 23:33:53 +00:00
top.ys	Pass -full to opt	2017-12-08 22:29:22 +00:00
uart.sv	Merge memory bus inputs/outputs in the port list	2017-12-12 21:15:11 +00:00