32-bit RISC-V system on chip for iCE40 FPGAs
b73a0155dd
Although the processor uses little-endian addressing, the memory bus itself is big-endian. (This simplifies the implementation of memory-mapped registers.) However, this does mean the contents of the RAM need to be in big-endian order, rather than little-endian order. $readmemh does not provide any control over byte order, so we previously swapped the byte order of progmem.hex with srec_cat in the Makefile. This commit changes the ram module to swap the byte order upon reading/writing. This removes the need to use srec_cat in the Makefile. Swapping the byte order in hardware shouldn't cause any performance impact as it just involves re-arranging wires. |
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| .gitignore | ||
| .gitlab-ci.yml | ||
| bus_arbiter.sv | ||
| clk_div.sv | ||
| ice40hx8k-b-evn.pcf | ||
| Makefile | ||
| progmem.c | ||
| progmem.lds | ||
| ram.sv | ||
| rv32.sv | ||
| rv32_alu.sv | ||
| rv32_branch.sv | ||
| rv32_decode.sv | ||
| rv32_execute.sv | ||
| rv32_fetch.sv | ||
| rv32_hazard.sv | ||
| rv32_mem.sv | ||
| rv32_opcodes.sv | ||
| rv32_regs.sv | ||
| start.s | ||
| sync.sv | ||
| top.sv | ||
| top.ys | ||
| uart.sv | ||