Commit graph

14 commits

Author SHA1 Message Date
Graham Edgecombe
4b6218c2a8 Add initial CSR support 2017-12-29 15:29:15 +00:00
Graham Edgecombe
0013935bb0 Split decode stage into smaller modules
This increases the number of LUTs slightly (by ~20), as the immediate
mux is now separate to the main control unit, but I think it's worth the
cost.

The imm output is also renamed to imm_value. This is consistent with
rs1_value and rs2_value, and avoids a collision with the new imm output,
which represents the type of immediate.
2017-12-27 14:05:09 +00:00
Graham Edgecombe
b01e81357d Re-use the main adder to implement the LUI, JAL and JALR instructions 2017-12-16 12:45:43 +00:00
Graham Edgecombe
22bce1bdeb Fix compatibility with iverilog
This commit:

 * changes the type of all output variables to logic
 * splits variable declaration and assignment
 * declares variables before modules that use the variables
2017-12-09 21:03:45 +00:00
Graham Edgecombe
e801556428 Replace localparams at the root level with defines
iverilog doesn't support localparams at the root level.
2017-12-09 10:44:39 +00:00
Graham Edgecombe
e7ae22bf31 Remove _ops.sv files 2017-12-07 22:37:58 +00:00
Graham Edgecombe
29e4c40af4 Remove clock input from ALU and branch PC mux 2017-12-07 22:37:58 +00:00
Graham Edgecombe
5516973b5f Fix bit shifting by numbers greater than 1 2017-12-07 22:37:58 +00:00
Graham Edgecombe
b1de4f3bb2 Fix ALU source multiplexers 2017-12-07 22:37:58 +00:00
Graham Edgecombe
bef709dc73 Replace always with always_ff 2017-12-02 18:29:51 +00:00
Graham Edgecombe
efb33456f9 Add include guards 2017-12-01 23:30:33 +00:00
Graham Edgecombe
5884a437b8 Add JAL/JALR support to the ALU 2017-12-01 23:02:50 +00:00
Graham Edgecombe
37d703c83e Add ALU control signals to the decoder 2017-12-01 23:02:50 +00:00
Graham Edgecombe
30b793cbaf Add ALU 2017-12-01 23:02:50 +00:00