32-bit RISC-V system on chip for iCE40 FPGAs

Graham Edgecombe 3ed53406a0 Move timing closure requirement to the flash target ... It's possible that some tools interact with the bitstream directly rather than the .asc files, and we may still want to run them even if timing closure is not met.		2017-12-07 22:37:58 +00:00
.gitignore	Store icebox_stat output in top.stat	2017-12-07 22:37:58 +00:00
clk_div.sv	Replace wire with logic	2017-12-07 22:37:58 +00:00
ice40hx8k-b-evn.pcf	Add serial flash, LED and UART pins	2017-12-01 23:25:06 +00:00
Makefile	Move timing closure requirement to the flash target	2017-12-07 22:37:58 +00:00
progmem.s	Use t0 register in demo program	2017-12-07 22:37:58 +00:00
ram.sv	Add memory address decoding	2017-12-07 22:37:58 +00:00
rv32.sv	Memory map the LEDs	2017-12-07 22:37:58 +00:00
rv32_alu.sv	Remove _ops.sv files	2017-12-07 22:37:58 +00:00
rv32_branch.sv	Remove _ops.sv files	2017-12-07 22:37:58 +00:00
rv32_decode.sv	Revert "Reset {rs1,rs2_out} when flushing the decode stage"	2017-12-07 22:37:58 +00:00
rv32_execute.sv	Pass forwarded rs1 value to the branch target mux	2017-12-07 22:37:58 +00:00
rv32_fetch.sv	Follow the standard naming/commenting conventions in hazard-related code	2017-12-07 22:37:58 +00:00
rv32_hazard.sv	Replace pointless if with assign in the hazard unit	2017-12-07 22:37:58 +00:00
rv32_mem.sv	Add memory bus and move data memory to a separate module	2017-12-07 22:37:58 +00:00
rv32_opcodes.sv	Add flush and stall inputs to every stage	2017-12-07 22:37:58 +00:00
rv32_regs.sv	Follow the standard naming/commenting conventions in hazard-related code	2017-12-07 22:37:58 +00:00
sync.sv	Add synchronizer module	2017-12-07 22:37:58 +00:00
top.sv	Add PLL	2017-12-07 22:37:58 +00:00
top.ys	Run abc twice to improve logic density	2017-12-07 22:37:58 +00:00