This reduces the amount of logic required and should speed the processor
up slightly, as the critical path had moved from the execute stage to
the branching logic in the mem/fetch stages.
This reduces the amount of logic slightly, and also removes the one
cycle delay between a CSR read and a subsequent instruction reading from
the destination register.
This increases the number of LUTs slightly (by ~20), as the immediate
mux is now separate to the main control unit, but I think it's worth the
cost.
The imm output is also renamed to imm_value. This is consistent with
rs1_value and rs2_value, and avoids a collision with the new imm output,
which represents the type of immediate.
This commit:
* changes the type of all output variables to logic
* splits variable declaration and assignment
* declares variables before modules that use the variables
