Graham Edgecombe
04dc25c5dc
Merge memory bus inputs/outputs in the port list
...
I don't think the control/data in/out split makes as much sense - it's
a convention much better suited to the pipeline stages.
2017-12-12 21:15:11 +00:00
Graham Edgecombe
22bce1bdeb
Fix compatibility with iverilog
...
This commit:
* changes the type of all output variables to logic
* splits variable declaration and assignment
* declares variables before modules that use the variables
2017-12-09 21:03:45 +00:00
Graham Edgecombe
02a742b3c9
Remove trailing comma in SB_IO declaration
...
Icarus treats this is an error.
2017-12-07 22:49:28 +00:00
Graham Edgecombe
6d638404f1
Add new memory-mapped UART
...
This implementation uses a simpler state machine than the previous
version.
The receiver still needs to be implemented.
2017-12-07 22:37:59 +00:00
Graham Edgecombe
bb5f2c8d8c
Fix ram_sel/leds_sel decoding
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Wildcards can only be used in casez statements - not in if statements.
2017-12-07 22:37:59 +00:00
Graham Edgecombe
82394bce1c
Add read_out signal to the memory bus
...
This is required to implement reads with side effects (e.g. reading from
the UART receive buffer).
2017-12-07 22:37:58 +00:00
Graham Edgecombe
cddfd0587d
Add loopback UART
2017-12-07 22:37:58 +00:00
Graham Edgecombe
3d26eb67ed
Synchronize the PLL locked output with the clock
2017-12-07 22:37:58 +00:00
Graham Edgecombe
26f6b88da8
Add PLL
2017-12-07 22:37:58 +00:00
Graham Edgecombe
a8225b8ebb
Fix clock connected to the LEDs flip flop
2017-12-07 22:37:58 +00:00
Graham Edgecombe
365d3e37c6
Memory map the LEDs
2017-12-07 22:37:58 +00:00
Graham Edgecombe
0be0da3917
Add memory address decoding
2017-12-07 22:37:58 +00:00
Graham Edgecombe
018faac560
Add memory bus and move data memory to a separate module
2017-12-07 22:37:58 +00:00
Graham Edgecombe
08c4451abf
Add clock divider
2017-12-07 22:37:58 +00:00
Graham Edgecombe
9de9955ad0
Connect lower 8 bits of x31 to the LEDs for debugging
2017-12-02 15:33:45 +00:00
Graham Edgecombe
3af3fb71a1
Add serial flash, LED and UART pins
2017-12-01 23:25:06 +00:00
Graham Edgecombe
9ca70b76a6
Remove redundant logic keyword from the top module
2017-12-01 23:02:50 +00:00
Graham Edgecombe
4a4dee334d
Add initial fetch/decode stages
2017-12-01 08:46:43 +00:00
