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41 commits

Author SHA1 Message Date
Graham Edgecombe
8024a6075f Move result zero/non-zero test to the execute stage 
This reduces the amount of logic required and should speed the processor
up slightly, as the critical path had moved from the execute stage to
the branching logic in the mem/fetch stages.
 2017-12-30 14:12:23 +00:00
Graham Edgecombe
6c964c75e5 Add static branch prediction 2017-12-30 13:48:14 +00:00
Graham Edgecombe
276688f9ef Move CSR access to the execute stage 
This reduces the amount of logic slightly, and also removes the one
cycle delay between a CSR read and a subsequent instruction reading from
the destination register.
 2017-12-30 11:34:14 +00:00
Graham Edgecombe
eac6a20040 Only stall the pipeline if rs1/rs2 are read 2017-12-29 20:37:02 +00:00
Graham Edgecombe
4b6218c2a8 Add initial CSR support 2017-12-29 15:29:15 +00:00
Graham Edgecombe
de1f936cdd Implement FENCE.I 2017-12-27 15:23:59 +00:00
Graham Edgecombe
0013935bb0 Split decode stage into smaller modules 
This increases the number of LUTs slightly (by ~20), as the immediate
mux is now separate to the main control unit, but I think it's worth the
cost.

The imm output is also renamed to imm_value. This is consistent with
rs1_value and rs2_value, and avoids a collision with the new imm output,
which represents the type of immediate.
 2017-12-27 14:05:09 +00:00
Graham Edgecombe
2b1e0de9de Propagate mem_fence signal through the pipeline 2017-12-26 16:46:01 +00:00
Graham Edgecombe
9b1e27cc0d Combine the instruction and data buses 2017-12-25 23:33:53 +00:00
Graham Edgecombe
7f81e495b3 Add write enable output to the memory bus 
This will be used by the bus arbiter and the hazard unit. We could use
the write_mask output, but this would introduce a longer delay.
 2017-12-17 20:47:17 +00:00
Graham Edgecombe
7ef3e831ce Prefix data bus wire names with data_ 2017-12-17 19:57:00 +00:00
Graham Edgecombe
b01e81357d Re-use the main adder to implement the LUI, JAL and JALR instructions 2017-12-16 12:45:43 +00:00
Graham Edgecombe
04dc25c5dc Merge memory bus inputs/outputs in the port list 
I don't think the control/data in/out split makes as much sense - it's
a convention much better suited to the pipeline stages.
 2017-12-12 21:15:11 +00:00
Graham Edgecombe
58ff5c9ec7 Rename rv32_hazard to rv32_hazard_unit 2017-12-12 21:04:33 +00:00
Graham Edgecombe
22bce1bdeb Fix compatibility with iverilog 
This commit:

 * changes the type of all output variables to logic
 * splits variable declaration and assignment
 * declares variables before modules that use the variables
 2017-12-09 21:03:45 +00:00
Graham Edgecombe
82394bce1c Add read_out signal to the memory bus 
This is required to implement reads with side effects (e.g. reading from
the UART receive buffer).
 2017-12-07 22:37:58 +00:00
Graham Edgecombe
460159a392 Rename rd_writeback to rd_write 
This is consistent with the mem_read and mem_write naming.
 2017-12-07 22:37:58 +00:00
Graham Edgecombe
36b7d33850 Read mem_{read,write}_en to mem_{read,write} 2017-12-07 22:37:58 +00:00
Graham Edgecombe
365d3e37c6 Memory map the LEDs 2017-12-07 22:37:58 +00:00
Graham Edgecombe
018faac560 Add memory bus and move data memory to a separate module 2017-12-07 22:37:58 +00:00
Graham Edgecombe
03ecd3a97d Remove unused mem_read_en output 2017-12-07 22:37:58 +00:00
Graham Edgecombe
da26f86f25 Remove two cycle load-use stall 
There's no need for it as we forward results from the writeback to the
execute stage.
 2017-12-07 22:37:58 +00:00
Graham Edgecombe
0c3b91e733 Fix load-use hazard logic 2017-12-07 22:37:58 +00:00
Graham Edgecombe
0acde319b0 Stall the decode stage if it is waiting on a load 2017-12-07 22:37:58 +00:00
Graham Edgecombe
965311c1e5 Add mem_ prefix to the hazard unit's branch_taken input 2017-12-07 22:37:58 +00:00
Graham Edgecombe
86022d42a5 Follow the standard naming/commenting conventions in hazard-related code 2017-12-07 22:37:58 +00:00
Graham Edgecombe
5ec95c00a2 Flush the decode/execute stages if a branch is taken 2017-12-07 22:37:58 +00:00
Graham Edgecombe
4c2c44e94d Add initial hazard unit 2017-12-07 22:37:58 +00:00
Graham Edgecombe
310c275ba2 Hard-wire stall and flush inputs to zero 2017-12-07 22:37:58 +00:00
Graham Edgecombe
83b7d1c9b7 Add 'from stage' comments if inputs are not from the previous stage 2017-12-07 22:37:58 +00:00
Graham Edgecombe
dd6e01fb5c Move result/mem_read_value mux to the mem stage 
This should reduce the logic required to forward the writeback rd_value
to the execute stage, which is on the critical path.
 2017-12-07 22:37:58 +00:00
Graham Edgecombe
8e2ce65ad9 Add operand forwarding to the execute stage 2017-12-07 22:37:58 +00:00
Graham Edgecombe
871e1f4a32 Add LB, LBU, LH, LHU, SB and SH instructions 2017-12-07 22:37:58 +00:00
Graham Edgecombe
9de9955ad0 Connect lower 8 bits of x31 to the LEDs for debugging 2017-12-02 15:33:45 +00:00
Graham Edgecombe
86f6e0eec1 Add branching support 2017-12-02 15:23:12 +00:00
Graham Edgecombe
4c68818134 Add writeback stage 2017-12-02 11:26:12 +00:00
Graham Edgecombe
3f8e64c65a Add memory access stage 2017-12-02 10:22:48 +00:00
Graham Edgecombe
efb33456f9 Add include guards 2017-12-01 23:30:33 +00:00
Graham Edgecombe
30b793cbaf Add ALU 2017-12-01 23:02:50 +00:00
Graham Edgecombe
ed238e5e9b Use -noautowire to avoid using logic in every input/output declaration 2017-12-01 18:49:48 +00:00
Graham Edgecombe
4a4dee334d Add initial fetch/decode stages 2017-12-01 08:46:43 +00:00