Graham Edgecombe
|
cc1f73e19e
|
Replace pointless if with assign in the hazard unit
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
bf6622d9f4
|
Add Egyptian multiplication demo program
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
281009a64c
|
Increase size of data RAM to 8 KB
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
018faac560
|
Add memory bus and move data memory to a separate module
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
03ecd3a97d
|
Remove unused mem_read_en output
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
da26f86f25
|
Remove two cycle load-use stall
There's no need for it as we forward results from the writeback to the
execute stage.
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
9541f198c2
|
Revert "Reset {rs1,rs2_out} when flushing the decode stage"
This reverts commit 144cbe996fab0596230d9b7d14c94373e8e5bbba.
It isn't required as we reset the rd_writeback_out register.
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
e7ae22bf31
|
Remove _ops.sv files
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
0c3b91e733
|
Fix load-use hazard logic
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
0c79ae6fc5
|
Pass forwarded rs1 value to the branch target mux
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
bd0a56118d
|
Pass forwarded rs2 value to the mem stage
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
0acde319b0
|
Stall the decode stage if it is waiting on a load
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
965311c1e5
|
Add mem_ prefix to the hazard unit's branch_taken input
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
9af1107041
|
Add comments to rv32_hazard.sv
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
86022d42a5
|
Follow the standard naming/commenting conventions in hazard-related code
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
5ec95c00a2
|
Flush the decode/execute stages if a branch is taken
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
4c2c44e94d
|
Add initial hazard unit
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
310c275ba2
|
Hard-wire stall and flush inputs to zero
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
70d72331a7
|
Order outputs consistently in the decode stage
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
02f1d705b7
|
Reset {rs1,rs2_out} when flushing the decode stage
This will prevent us needing to stall the pipeline for a load
instruction if the rs1/rs2 registers happened to match the rd register.
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
eff39ad19b
|
Add flush and stall inputs to every stage
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
29e4c40af4
|
Remove clock input from ALU and branch PC mux
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
3539f67764
|
Replace wire with logic
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
4bacded87a
|
Fix always_comb block in rv32_branch.sv
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
cc89d3f93a
|
Replace tabs with spaces in rv32_mem.sv
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
83b7d1c9b7
|
Add 'from stage' comments if inputs are not from the previous stage
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
dd6e01fb5c
|
Move result/mem_read_value mux to the mem stage
This should reduce the logic required to forward the writeback rd_value
to the execute stage, which is on the critical path.
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
8e2ce65ad9
|
Add operand forwarding to the execute stage
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
5516973b5f
|
Fix bit shifting by numbers greater than 1
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
acbac650bf
|
Mark the lower 27 bits of shamt as don't care
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
871e1f4a32
|
Add LB, LBU, LH, LHU, SB and SH instructions
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
e2a533babb
|
Access data memory on negative clock edge
This will allow shifting, sign extension and zero extension logic to be
placed after reads, so we can add support for the LB, LBU, LH and LHU
opcodes.
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
ff22a4682a
|
Ignore LSB of JALR target address
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
ee768c51d4
|
Add FENCE and FENCE.I instructions
Both are currently NOPs as the implementation is currently in-order and
has separate instruction and data memories.
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
141912b568
|
Use 4 space indentation in the assembly file for consistency
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
08c4451abf
|
Add clock divider
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
88928aa1b2
|
Fix immediate decoding in J-type instructions
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
eaf68f8d1d
|
Run abc twice to improve logic density
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
b1de4f3bb2
|
Fix ALU source multiplexers
|
2017-12-07 22:37:58 +00:00 |
|
Graham Edgecombe
|
85ba0c7faa
|
Remove read_value_out enable input
|
2017-12-07 22:37:23 +00:00 |
|
Graham Edgecombe
|
bef709dc73
|
Replace always with always_ff
|
2017-12-02 18:29:51 +00:00 |
|
Graham Edgecombe
|
eb053503f7
|
Populate instr_mem with a test assembly program
|
2017-12-02 18:07:37 +00:00 |
|
Graham Edgecombe
|
9de9955ad0
|
Connect lower 8 bits of x31 to the LEDs for debugging
|
2017-12-02 15:33:45 +00:00 |
|
Graham Edgecombe
|
86f6e0eec1
|
Add branching support
|
2017-12-02 15:23:12 +00:00 |
|
Graham Edgecombe
|
4c68818134
|
Add writeback stage
|
2017-12-02 11:26:12 +00:00 |
|
Graham Edgecombe
|
062462eeb3
|
Fix indentation in rv32_decode.sv
|
2017-12-02 10:23:11 +00:00 |
|
Graham Edgecombe
|
3f8e64c65a
|
Add memory access stage
|
2017-12-02 10:22:48 +00:00 |
|
Graham Edgecombe
|
efb33456f9
|
Add include guards
|
2017-12-01 23:30:33 +00:00 |
|
Graham Edgecombe
|
3af3fb71a1
|
Add serial flash, LED and UART pins
|
2017-12-01 23:25:06 +00:00 |
|
Graham Edgecombe
|
9ca70b76a6
|
Remove redundant logic keyword from the top module
|
2017-12-01 23:02:50 +00:00 |
|