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Author	SHA1	Message	Date
Graham Edgecombe	02a742b3c9	Remove trailing comma in SB_IO declaration ... Icarus treats this is an error.	2017-12-07 22:49:28 +00:00
Graham Edgecombe	9f036f6630	Add UART demo program	2017-12-07 22:37:59 +00:00
Graham Edgecombe	66089359fe	Make the meaning of the TX write ready status bit clearer	2017-12-07 22:37:59 +00:00
Graham Edgecombe	02909b1f98	Add receive support to the UART	2017-12-07 22:37:59 +00:00
Graham Edgecombe	4d9d405c05	Fix TX ready output	2017-12-07 22:37:59 +00:00
Graham Edgecombe	6d638404f1	Add new memory-mapped UART ... This implementation uses a simpler state machine than the previous version. The receiver still needs to be implemented.	2017-12-07 22:37:59 +00:00
Graham Edgecombe	bb5f2c8d8c	Fix ram_sel/leds_sel decoding ... Wildcards can only be used in casez statements - not in if statements.	2017-12-07 22:37:59 +00:00
Graham Edgecombe	82394bce1c	Add read_out signal to the memory bus ... This is required to implement reads with side effects (e.g. reading from the UART receive buffer).	2017-12-07 22:37:58 +00:00
Graham Edgecombe	460159a392	Rename rd_writeback to rd_write ... This is consistent with the mem_read and mem_write naming.	2017-12-07 22:37:58 +00:00
Graham Edgecombe	36b7d33850	Read mem_{read,write}_en to mem_{read,write}	2017-12-07 22:37:58 +00:00
Graham Edgecombe	cddfd0587d	Add loopback UART	2017-12-07 22:37:58 +00:00
Graham Edgecombe	3d26eb67ed	Synchronize the PLL locked output with the clock	2017-12-07 22:37:58 +00:00
Graham Edgecombe	3ed53406a0	Move timing closure requirement to the flash target ... It's possible that some tools interact with the bitstream directly rather than the .asc files, and we may still want to run them even if timing closure is not met.	2017-12-07 22:37:58 +00:00
Graham Edgecombe	b4e0e6ceb0	Store icebox_stat output in top.stat ... This also takes a long time to generate.	2017-12-07 22:37:58 +00:00
Graham Edgecombe	967f3d1414	Delete pll.sv in the clean target	2017-12-07 22:37:58 +00:00
Graham Edgecombe	560f45d3ca	Require timing closure to be met before creating the bitstream	2017-12-07 22:37:58 +00:00
Graham Edgecombe	260c0429bd	Store timing report in top.rpt ... This stops us needing to re-generate it if the design hasn't changed.	2017-12-07 22:37:58 +00:00
Graham Edgecombe	26f6b88da8	Add PLL	2017-12-07 22:37:58 +00:00
Graham Edgecombe	a8225b8ebb	Fix clock connected to the LEDs flip flop	2017-12-07 22:37:58 +00:00
Graham Edgecombe	998dd0f0ba	Add synchronizer module	2017-12-07 22:37:58 +00:00
Graham Edgecombe	3be5990b17	Use t0 register in demo program	2017-12-07 22:37:58 +00:00
Graham Edgecombe	365d3e37c6	Memory map the LEDs	2017-12-07 22:37:58 +00:00
Graham Edgecombe	0be0da3917	Add memory address decoding	2017-12-07 22:37:58 +00:00
Graham Edgecombe	cc1f73e19e	Replace pointless if with assign in the hazard unit	2017-12-07 22:37:58 +00:00
Graham Edgecombe	bf6622d9f4	Add Egyptian multiplication demo program	2017-12-07 22:37:58 +00:00
Graham Edgecombe	281009a64c	Increase size of data RAM to 8 KB	2017-12-07 22:37:58 +00:00
Graham Edgecombe	018faac560	Add memory bus and move data memory to a separate module	2017-12-07 22:37:58 +00:00
Graham Edgecombe	03ecd3a97d	Remove unused mem_read_en output	2017-12-07 22:37:58 +00:00
Graham Edgecombe	da26f86f25	Remove two cycle load-use stall ... There's no need for it as we forward results from the writeback to the execute stage.	2017-12-07 22:37:58 +00:00
Graham Edgecombe	9541f198c2	Revert "Reset {rs1,rs2_out} when flushing the decode stage" ... This reverts commit 144cbe996fab0596230d9b7d14c94373e8e5bbba. It isn't required as we reset the rd_writeback_out register.	2017-12-07 22:37:58 +00:00
Graham Edgecombe	e7ae22bf31	Remove _ops.sv files	2017-12-07 22:37:58 +00:00
Graham Edgecombe	0c3b91e733	Fix load-use hazard logic	2017-12-07 22:37:58 +00:00
Graham Edgecombe	0c79ae6fc5	Pass forwarded rs1 value to the branch target mux	2017-12-07 22:37:58 +00:00
Graham Edgecombe	bd0a56118d	Pass forwarded rs2 value to the mem stage	2017-12-07 22:37:58 +00:00
Graham Edgecombe	0acde319b0	Stall the decode stage if it is waiting on a load	2017-12-07 22:37:58 +00:00
Graham Edgecombe	965311c1e5	Add mem_ prefix to the hazard unit's branch_taken input	2017-12-07 22:37:58 +00:00
Graham Edgecombe	9af1107041	Add comments to rv32_hazard.sv	2017-12-07 22:37:58 +00:00
Graham Edgecombe	86022d42a5	Follow the standard naming/commenting conventions in hazard-related code	2017-12-07 22:37:58 +00:00
Graham Edgecombe	5ec95c00a2	Flush the decode/execute stages if a branch is taken	2017-12-07 22:37:58 +00:00
Graham Edgecombe	4c2c44e94d	Add initial hazard unit	2017-12-07 22:37:58 +00:00
Graham Edgecombe	310c275ba2	Hard-wire stall and flush inputs to zero	2017-12-07 22:37:58 +00:00
Graham Edgecombe	70d72331a7	Order outputs consistently in the decode stage	2017-12-07 22:37:58 +00:00
Graham Edgecombe	02f1d705b7	Reset {rs1,rs2_out} when flushing the decode stage ... This will prevent us needing to stall the pipeline for a load instruction if the rs1/rs2 registers happened to match the rd register.	2017-12-07 22:37:58 +00:00
Graham Edgecombe	eff39ad19b	Add flush and stall inputs to every stage	2017-12-07 22:37:58 +00:00
Graham Edgecombe	29e4c40af4	Remove clock input from ALU and branch PC mux	2017-12-07 22:37:58 +00:00
Graham Edgecombe	3539f67764	Replace wire with logic	2017-12-07 22:37:58 +00:00
Graham Edgecombe	4bacded87a	Fix always_comb block in rv32_branch.sv	2017-12-07 22:37:58 +00:00
Graham Edgecombe	cc89d3f93a	Replace tabs with spaces in rv32_mem.sv	2017-12-07 22:37:58 +00:00
Graham Edgecombe	83b7d1c9b7	Add 'from stage' comments if inputs are not from the previous stage	2017-12-07 22:37:58 +00:00
Graham Edgecombe	dd6e01fb5c	Move result/mem_read_value mux to the mem stage ... This should reduce the logic required to forward the writeback rd_value to the execute stage, which is on the critical path.	2017-12-07 22:37:58 +00:00