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Author SHA1 Message Date
Graham Edgecombe
63cd024d5c Fix instret rollover 2017-12-29 16:23:33 +00:00
Graham Edgecombe
0939363a3f Add rdcycle demo 2017-12-29 16:09:41 +00:00
Graham Edgecombe
20de15c3e5 Pass -Os to gcc 2017-12-29 16:09:19 +00:00
Graham Edgecombe
0bc2871ded Link with gcc instead of ld 2017-12-29 15:48:16 +00:00
Graham Edgecombe
4b6218c2a8 Add initial CSR support 2017-12-29 15:29:15 +00:00
Graham Edgecombe
de1f936cdd Implement FENCE.I 2017-12-27 15:23:59 +00:00
Graham Edgecombe
0013935bb0 Split decode stage into smaller modules 
This increases the number of LUTs slightly (by ~20), as the immediate
mux is now separate to the main control unit, but I think it's worth the
cost.

The imm output is also renamed to imm_value. This is consistent with
rs1_value and rs2_value, and avoids a collision with the new imm output,
which represents the type of immediate.
 2017-12-27 14:05:09 +00:00
Graham Edgecombe
2b1e0de9de Propagate mem_fence signal through the pipeline 2017-12-26 16:46:01 +00:00
Graham Edgecombe
f8b8842abc Bump FREQ_PLL to 36 MHz again 2017-12-26 14:40:54 +00:00
Graham Edgecombe
b73a0155dd Swap byte order in the ram module 
Although the processor uses little-endian addressing, the memory bus
itself is big-endian. (This simplifies the implementation of
memory-mapped registers.)

However, this does mean the contents of the RAM need to be in big-endian
order, rather than little-endian order. $readmemh does not provide any
control over byte order, so we previously swapped the byte order of
progmem.hex with srec_cat in the Makefile.

This commit changes the ram module to swap the byte order upon
reading/writing. This removes the need to use srec_cat in the Makefile.
Swapping the byte order in hardware shouldn't cause any performance
impact as it just involves re-arranging wires.
 2017-12-26 14:15:12 +00:00
Graham Edgecombe
3c2f7518ec Add new 'hello world' demo program 2017-12-26 13:46:20 +00:00
Graham Edgecombe
2ba26fc7e6 Switch from big- to little-endian ordering in the memory access stage 
The previous implementation mistakenly used big-endian instead of
little-endian.
 2017-12-26 13:40:55 +00:00
Graham Edgecombe
b578251132 Add rodata to the linker script 2017-12-25 23:42:32 +00:00
Graham Edgecombe
9b1e27cc0d Combine the instruction and data buses 2017-12-25 23:33:53 +00:00
Graham Edgecombe
7f81e495b3 Add write enable output to the memory bus 
This will be used by the bus arbiter and the hazard unit. We could use
the write_mask output, but this would introduce a longer delay.
 2017-12-17 20:47:17 +00:00
Graham Edgecombe
7ef3e831ce Prefix data bus wire names with data_ 2017-12-17 19:57:00 +00:00
Graham Edgecombe
b01e81357d Re-use the main adder to implement the LUI, JAL and JALR instructions 2017-12-16 12:45:43 +00:00
Graham Edgecombe
135a081fd4 Remove unused clk_div.sv include 2017-12-16 11:32:32 +00:00
Graham Edgecombe
bfbe3be490 Add FREQ macro to avoid hard-coding 36 MHz 2017-12-15 20:21:12 +00:00
Graham Edgecombe
e4e2e65293 Port example program to C 2017-12-15 20:08:55 +00:00
Graham Edgecombe
d97f8c5e8e Add yosys-config --datdir workaround 
The yosys-git AUR package doesn't set the PREFIX variable correctly.
 2017-12-15 18:35:26 +00:00
Graham Edgecombe
9f8ca8c496 Add GitLab CI config 2017-12-15 18:31:48 +00:00
Graham Edgecombe
a713290deb Add MRET and WFI to the decoder 
No TODO in the WFI block as it will be implemented as a no-op.
 2017-12-14 23:53:49 +00:00
Graham Edgecombe
c61234f7e4 Order ECALL/EBREAK consistently 2017-12-14 23:53:02 +00:00
Graham Edgecombe
d5c87dacf6 Add MRET and WFI instruction encoding 
I'm probably going to implement a subset of the privileged ISA for
interrupt support.
 2017-12-14 23:46:18 +00:00
Graham Edgecombe
5f84ff150b Simplify giant case statement in the decoder 
This makes it easier to add special instructions (e.g. ECALL/EBREAK)
that have unusual encodings (e.g. the funct12 field).
 2017-12-12 22:42:47 +00:00
Graham Edgecombe
d6f5bb2218 Add initial support for SYSTEM instructions to the decoder 2017-12-12 22:41:01 +00:00
Graham Edgecombe
9259065656 Rename check target to syntax 
check is normally used for automated tests.
 2017-12-12 21:20:49 +00:00
Graham Edgecombe
04dc25c5dc Merge memory bus inputs/outputs in the port list 
I don't think the control/data in/out split makes as much sense - it's
a convention much better suited to the pipeline stages.
 2017-12-12 21:15:11 +00:00
Graham Edgecombe
f571ab29eb Rename rv32_branch to rv32_branch_unit 2017-12-12 21:05:02 +00:00
Graham Edgecombe
58ff5c9ec7 Rename rv32_hazard to rv32_hazard_unit 2017-12-12 21:04:33 +00:00
Graham Edgecombe
f19d41c8a2 Replace $(TOP).bin with $(BIN) 2017-12-10 14:10:51 +00:00
Graham Edgecombe
b8e848cb0e Add SV variable to replace $(TOP).sv 2017-12-10 14:10:33 +00:00
Graham Edgecombe
8e1f64eea0 Add progmem_syn.hex dependency to the check target 2017-12-10 09:25:37 +00:00
Graham Edgecombe
9c8dfd1b82 Replace top.sv with $(TOP).sv 2017-12-10 09:25:18 +00:00
Graham Edgecombe
0306c4dc72 Add iverilog syntax check target 2017-12-09 21:33:51 +00:00
Graham Edgecombe
22bce1bdeb Fix compatibility with iverilog 
This commit:

 * changes the type of all output variables to logic
 * splits variable declaration and assignment
 * declares variables before modules that use the variables
 2017-12-09 21:03:45 +00:00
Graham Edgecombe
de54271076 Fix width of RV32_BRANCH_OP constants 2017-12-09 10:46:08 +00:00
Graham Edgecombe
e801556428 Replace localparams at the root level with defines 
iverilog doesn't support localparams at the root level.
 2017-12-09 10:44:39 +00:00
Graham Edgecombe
bf7b1bef4f Pass -full to opt 
Reduces the number of LUTs slightly.
 2017-12-08 22:29:22 +00:00
Graham Edgecombe
02a742b3c9 Remove trailing comma in SB_IO declaration 
Icarus treats this is an error.
 2017-12-07 22:49:28 +00:00
Graham Edgecombe
9f036f6630 Add UART demo program 2017-12-07 22:37:59 +00:00
Graham Edgecombe
66089359fe Make the meaning of the TX write ready status bit clearer 2017-12-07 22:37:59 +00:00
Graham Edgecombe
02909b1f98 Add receive support to the UART 2017-12-07 22:37:59 +00:00
Graham Edgecombe
4d9d405c05 Fix TX ready output 2017-12-07 22:37:59 +00:00
Graham Edgecombe
6d638404f1 Add new memory-mapped UART 
This implementation uses a simpler state machine than the previous
version.

The receiver still needs to be implemented.
 2017-12-07 22:37:59 +00:00
Graham Edgecombe
bb5f2c8d8c Fix ram_sel/leds_sel decoding 
Wildcards can only be used in casez statements - not in if statements.
 2017-12-07 22:37:59 +00:00
Graham Edgecombe
82394bce1c Add read_out signal to the memory bus 
This is required to implement reads with side effects (e.g. reading from
the UART receive buffer).
 2017-12-07 22:37:58 +00:00
Graham Edgecombe
460159a392 Rename rd_writeback to rd_write 
This is consistent with the mem_read and mem_write naming.
 2017-12-07 22:37:58 +00:00
Graham Edgecombe
36b7d33850 Read mem_{read,write}_en to mem_{read,write} 2017-12-07 22:37:58 +00:00